Another thermal enhancement for QFP packages is an internal spreader. When planes are not available, it is common practice to couple the exposed pad to a large metal “radiator” pad (perhaps 25 x 25 mm or larger) on the other side of the printed circuit board. The specification of the device should be documented to show whether the exposed pad can be electrically connected to the ground or to one of the power planes. To create such a model, it is important to ask whether the component supplier is providing the θ jc to the exposed pad of the package rather than the top of the package.įor the exposed pad package to achieve the performance indicated by the θ ja (on 2s2p board) that is quoted by the component supplier, it is important that there is an array of vias under the exposed pad and that the vias are connected to one or more planes in the printed circuit board. For the exposed pad package soldered to the printed circuit board, adequate accuracy can usually be obtained by modeling the thermal resistance from the die to the printed circuit board. Two resistor models can be created from the θ jb (Junction to Board Thermal Resistance) and θ jc (Junction to Case Thermal Resistance). EP-SOIC or EP-QFP with the die attached to a pad visible from the bottom of the package.One would normally model SOIC and QFP packages with two resistor models if a more detailed model is not available. For instance, a 64 10 x 10 EP-LQFP (Exposed Pad – Low Profile Quad Flat Package) with a die size of 4.4 x 3.7 mm had a θ ja in natural convection on a 2s2p board of 26☌/W compared to 47☌/W for the standard package.įigure 2. By allowing the leadframe pad to be soldered to the printed circuit board, much improved thermal performance of the package is obtained. Recently, exposed pad versions of this package have been used (Figure 2). Because of the need to tool a special leadframe for each device, this enhancement is not common. This provides a direct thermal path from the flag to the printed circuit board. SOIC or QFP cross section.The first enhancement that is used for these packages is a “thermal lead” or “fused lead”, which is a lead that is connected to the flag. To improve the mechanical integrity of the package during a board soldering process, the leadframe pad size is normally minimized.įigure 1. The thermal performance of the SOIC (Small Outline Integrated Circuit) and QFP (Quad Flat Package) style package (Figure 1) is determined to a large extent by the package size, the leadframe pad for the die (commonly called the die pad or flag) and die size. high electrical performance flip chip packages.low lead count with low cost requirements.For this discussion, we will consider three groups of packages: The package choice is driven by the number of i/o connections required, electrical performance (inductance or controlled impedance), power delivery design, thermal requirements, customer demand (matching of previous products) and cost. The list of packages in Table 1 omits a number of specialized packages including PGA (Pin Grid Array Packages), SIP (Single Inline Power Packages), ceramic and plastic DIP (Dual Inline Packages), ceramic BGA (Ball Grid Array) packages, CLCC (Ceramic Leadless Chip Carrier) and all the chip scale and direct chip attach configurations. The readers of this publication should recognize the limitations of using standard thermal resistances in estimating thermal performance. The thermal test boards are also specified in this series of specifications. Both the qja values determined on a single layer (1s) board and on a four metal layer (2s2p or 2 signals and 2 planes) board are provided. A guideline and short tutorial on the use of the resistances and the specifications is found among the JEDEC documents. As a method of comparing and describing the thermal performance of the packages, the standard thermal resistances as defined by JEDEC are used. List of Common Integrated Circuit PackagesThe data in Table 1 list the typical range of Junction-to-Ambient Thermal Resistance (θ ja) observed for some common integrated circuit packages. For this discussion, the i/o count will include the power and ground connections. For this article, the number of connections of the package to the next level interconnect (the printed circuit board) are abbreviated as i/o for input/output. This review article will attempt to describe the most common thermal enhancements currently available. With such a broad range of interesting packaging to consider, it is no wonder that any simple generalizations will always find exceptions. Integrated circuits range in power consumption from mW (or maybe microwatts) to hundreds of Watts with the number of electrical connections to the next level packaging ranging from eight to over 1,000.
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